The present invention relates to dynamically isolated smart power integrated circuits.
A large amount of effort has been devoted to integrating high-density small-signal devices on a single integrated circuit with power devices. Such integrated circuits are commonly referred to as "smart power" circuits. However, the incompatibilities between vertical and planar processes have caused many difficulties in achieving such integration. Some general review of this class of integrated circuits can be found in Wrathall et al., "Integrated Circuits for the Control of High Power," 1983 IEDM Technical Digest, paper no. 16.1, at pp. 408ff, which is hereby incorporated by reference, and in Baliga, "An overview of smart power technology," 38 IEEE TRANSACTIONS ON ELECTRON DEVICES 1568 (1991), and references cited therein, all of which are hereby incorporated by reference. Reference is also made to Berta et al., "A simplified low-voltage smart power technology," 12 IEEE ELECTRON DEVICE LETTERS 465 (1991). Such integrated circuits are desirable for many applications, including but not limited to linear voltage regulators, switching voltage regulators, AC motor control, fluorescent light ballasts, automotive controls, etc.
Such smart power chips normally include an isolation region designed to ensure electric isolation of the individual components, and therefore correct operation of the device. For simplicity of fabrication, this isolation region is typically a semiconductor region (such as region 3 in FIG. 1 ) which is doped to provide junction isolation. For this isolation region to fulfill its function, it is necessary that both of its junctions be normally reverse biased. This is achieved by connecting the isolation region to a potential not greater than the minimum voltage applied to the device. Therefore, since the terminal with potential lower than the supply battery is normally grounded, the isolation region is also grounded for the above reasons.
Note that this junction isolation defines a parasitic transistor. In the sample structure of FIG. 1, the parasitic transistor is predominantly vertical, and is defined by N-type region 4 (the logic device's collector), which overlies P-type region 3 (the isolation region), which overlies N-type regions 1 and 2 (the power device's collector). Typical applied voltages of these regions, in normal operation, would be a few Volts on region 4 (from connection C.sub.1), ground potential on region 3, and several tens of volts on regions 1 and 2 (from terminal C.sub.p). Thus, if this parasitic transistor were to turn on, region 4 could act as an emitter, and the large voltage difference between terminal C.sub.p and C.sub.1 could cause very large currents, and destruction of portions of the integrated circuit.
Merely grounding terminal ISO, in a junction isolation structure like that of FIG. 1, is not effective in many cases. For example, it can happen that, upon the occurrence of spurious pulses on the power supply lines, or upon the occurrence of transients due to switching of an inductive load, the voltage (Vout) of the collector (C.sub.p) of the power transistor displays transiently negative values. This common occurrence is referred to as a "subground" situation.
To prevent the parasitic vertical transistor from going into conduction when a subground situation occurs, there has been conceived a dynamic isolation circuit which calls for keeping the connection of the isolation region grounded when the Vout is positive and switching the grounding into a connection to the power transistor collector when the Vout displays subground transients. This circuit is described in U.S. Pat. No. 5,159,202, corresponding to French patent application no. 89/16144, which is hereby incorporated by reference.
However, the present inventors have discovered that this dynamic isolation circuit does not prevent the parasitic vertical transistor from going into conduction, in some cases, when negative voltage transients are applied to the control circuit.
The present invention provides a smart power integrated circuit with a more complex dynamic isolation circuit. This more complex dynamic isolation circuit holds the isolation region to the lowest potential present on-chip. This is done on the fly, preferably by using MOSFETs to reconnect the isolation region to one of at least two collector potentials whenever any of them has a subground voltage.
In the presently preferred embodiment, as in the conventional device structure of FIG. 1, a P-type isolation region surrounds the small signal devices (npn bipolar transistors and possibly other devices). This isolation region is held at ground in normal operation; but one or more pilot circuits continually monitor the collector voltages of the small-signal and power npn transistors, and instantly reconnect this isolation region, in real time, to the lowest collector voltage, whenever any of the collector voltages go below ground. Preferably a large capacitor provides a dedicated supply to the pilot circuit, so that the reconnection operation can proceed even when a power supply glitch occurs.
The present invention allows achievement of at least the following advantages:
provision of a semiconductor electronic device with dynamic isolation circuit ensuring isolation conditions even with negative voltage transients on the control circuit,
reduction of implementation costs of the described dynamic isolation principle by means of integrated structures not requiring a polycrystalline silicon process,
extension and optimization of the decisional circuitry part dedicated to piloting the synchronous switches which provide the dynamic isolation, and
dynamic isolation of different isolation regions not connected together with variation of the voltage applied to the common substrate.
In the presently preferred embodiment, the semiconductor electronic device with dynamic isolation includes at least one power transistor and at least one control circuit integrated monolithically in the same chip, and also: one isolation region designed to isolate the individual components of the control circuit from each other and from the power transistor, a first switch designed to connect the isolation region with a ground node, a second switch designed to connect the isolation region with the collector or drain of the power transistor, a pilot circuit connected with the collector or drain of the power transistor, with the ground node and with the first and second switches which, depending on whether the collector or drain has potential greater or less respectively than that of ground, commands closing of the first or second switch respectively, there is present a third switch (S3) designed to connect the isolation region with a region of a control circuit transistor, the pilot circuit is connected with the third switch (S3) and with the region of the control circuit transistor and commands closing of the third switch and opening of the first when the region of the control circuit transistor has potential less than that of ground. Other inventive solutions are indicated below in the claims.